Final SoCKET Workshop Toulouse, 23-24 November 2011 (IRIT, Campus de Rangueil)

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*   Program   *

23 November

10h - 10h30 Welcome and presentation of the SoCKET project (V.Lefftz, Astrium), slides

10h30 - 12h Description of the industrial case studies

∗ Avionics flight control remote module (P.Moreau, Airbus Operations S.A.S.), slides

∗ Space high resolution image processing (V.Lefftz, Astrium), slides

∗ Pedestrian tracking with smart cameras (P.Brelet, Thales Research & Technology), slides

∗ Controller for an absolute scalar magnetometer (J.Bertrand, A.Boness, CNES), slides

∗ System for secure communication (P.Gouriou, Maya), slides

∗ Synthesis of critical embedded systems needs (V.Lefftz, Astrium), slides

Lunch

13h30 - 14h20 Tutorial "SoC modeling with SystemC TLM" (L.Maillet-Contoz, STMicroelectronics), slides

14h20 - 15h10 Tutorial "IP-XACT for critical system assembly and requirements traceability" (E.Vaumorin and R.Lucas, Magillem Design Services), slides

Break

15h30 - 16h20 Tutorial "High-level synthesis" (P.Coussy, Lab-STICC UBS), slides

16h20- 17h10 Tutorial "Assertion-Based Verification (ABV): Verification of logical and temporal properties" (L.Pierre, TIMA Univ. Grenoble), slides

17h10 - 18h Tutorial "Worst Case Execution Time: theory and practice" (H.Cassé, IRIT Univ. Toulouse), slides

24 November

8h - 9h Presentation of the proposed design flow, and application to the different case studies (L.Maillet-Contoz, STMicroelectronics), slides

9h - 10h45 SystemC modeling in the design flow

A SystemC/TLM based design flow for embedded airborne electronic equipment development, L.Letellier and P.Moreau (Airbus Operations S.A.S.), slides

Use of SystemC/TLM virtual platforms for the exploration, the specification and the validation of critical embedded SoC's, A.Lefèvre et A.Berjaoui (Astrium), slides

Architecture exploration and optimisation of a flexible signal processing unit, A.Boness (CNES), slides

Modeling of a smart camera system, P.Brelet (Thales Research & Technology), slides

Break

11h15 - 12h IP-XACT in the design flow

IP-Xact in the design flow for embedded airborne electronic equipment development, L.Letellier and P.Moreau (Airbus Operations S.A.S.), slides

Case of a smart camera system, P.Brelet (Thales Research & Technology), slides

Lunch

13h30 - 14h20 High-level synthesis in the design flow

Use of behavioural synthesis for architecture exploration and logical synthesis of hardware IPs, J.Lachaize (Astrium), slides

Exploration and application deployment on a SoC: efficient application validation, P.Brelet (Thales Research & Technology), slides

14h20 - 15h20 Verification in the design flow

Assertion-Based Verification in the avionics context: verification of safety requirements, L.Letellier and P.Moreau (Airbus Operations S.A.S.), L.Pierre (TIMA Univ. Grenoble) , slides

Assertion-Based Verification in the space context: verification of correctness requirements, V.Lefftz (Astrium), L.Pierre (TIMA Univ. Grenoble) , slides

Verification of software properties: scheduling analysis and worst case execution time, A.Boness (CNES) , slides

15h20 - 15h40 Debug in the design flow

Description for a system for secure communication, P.Gouriou (Maya), slides

15h40 - 16h20 Presentation of the demonstrations

16h20 - 18h Break and demonstrations

High-Level Synthesis: an efficient solution to design hardware accelerators in SoC (Lab-STICC UBS), slides

FPGA implementation of the DSP unit and model of a magnetometric probe (CNES), slides

Automatic and efficient assertion-based verification for SystemC TLM hardware/software platforms (Airbus Operations S.A.S., Astrium, TIMA Univ. Grenoble)

Demonstration of object detection on a SoC (Thales Research & Technology)